In recent automobiles, networks of open drain (wired OR) forms, such as an ISO-9141 (a K line) and an LIN (Local Interconnect Network), are utilized as in-vehicle communication networks. Since such networks do not employ differential communication, they can be easily configured by a few numbers of wirings, and are frequently used for a system with a relatively low communication speed. A communication speed of the LIN is approximately 20 Kbps, and a communication speed of the K line is approximately 100 Kbps.
Generally, for ensuring safety, high reliability is required for communication networks applied to automobiles etc. In a system in which a number of communication networks and power supply wirings are concentrated in a closed environment, such as an automobile, EMI (Electro-Magnetic Interference) that a communication line (wire harness) radiates becomes a noise source. Accordingly, other systems must be prevented from malfunctioning due to this noise. Namely, in order to prevent systems other than a noise radiation source from malfunctioning by noise, a technique to dull a communication waveform by, for example, slew rate control is used in a communication line. As a result of this, a harmonic component in the communication waveform that acts as EMI noise can be suppressed.
In addition, the above-described communication line also serves as an antenna that receives EMI radiated by the other systems. Therefore, simultaneous pursuit of EMS (Electro-Magnetic Susceptibility) not to cause malfunction, such as the output circuit itself losing communication data when the antenna receives the EMI, is also an essential requirement.
There will be described an example of a circuit that performs slew rate control of a communication waveform used for noise suppression (Patent Literature 1). FIG. 9 is a block diagram showing a configuration of a slew rate output circuit 500. As shown in FIG. 9, the slew rate output circuit 500 includes a slew rate control circuit 51, an output circuit 52, and an output terminal Tout. A load RL is connected between the output terminal Tout and a power supply line Vdd. Power is supplied to the slew rate output circuit 500 from a power supply line Vcc.
FIG. 10 is a circuit diagram showing the configuration of the slew rate output circuit 500. Hereinafter, the configuration and operation of the slew rate output circuit 500 will be described with reference to FIG. 10. The slew rate output circuit 500 has an N-channel output transistor Q0 the source electrode of which has been grounded, and the load RL connected between the power supply line Vdd and the drain electrode thereof. The slew rate output circuit 500 is the open drain type slew rate output circuit that performs charge and discharge control of gate electrode capacitances Cdg and Cgs of the output transistor Q0 by two constant currents IrH and IrL respectively from a CS51 and a CS52.
When changing from a low level to a high level, an input pulse signal Vin is inverted by inverters INV51 and INV52, and gates of a P-channel transistor Q1 and an N-channel transistor Q2 both become the low level. Therefore, the P-channel transistor Q1 becomes an on state, the N-channel transistor Q2 becomes an off state, and the gate electrode capacitances Cdg and Cgs of the output transistor Q0 are charged by the constant current IrH from the constant current source CS51. As a result of it, a gate voltage Vgate gradually becomes the high level, and the output transistor Q0 slowly becomes the on state. When the input pulse signal Vin shifts from the high level to the low level, the P-channel transistor Q1 becomes the off state, the N-channel transistor Q2 becomes the on state, and the gate electrode capacitances Cdg and Cgs of the output transistor Q0 are discharged by the constant current IrL from the constant current source CS52. As a result of it, the gate voltage Vgate gradually becomes the low level, and the output transistor Q0 slowly becomes the off state.
FIG. 11 is a timing chart showing operation of the slew rate output circuit 500. As shown in FIG. 11, not only a rise time of the gate voltage Vgate but a fall time of the output voltage Vout change depending on the gate electrode capacitances Cdg and Cgs of the output transistor Q0, and a value of the constant current IrH. In addition, not only a fall time of the gate voltage Vgate but also a rise time of the output voltage Vout change depending on a value of the constant current IrL. This is because charge and discharge times of the gate electrode capacitances Cdg and Cgs of the output transistor Q0 change depending on the constant currents IrH and IrL. Namely, the slew rate output circuit 500 has achieved the above-mentioned slew rate control by controlling the values of the constant currents IrH and IrL.
In addition to that, a drive circuit has been proposed that can easily control a slew rate while suppressing a circuit size (Patent Literature 2).